1. Field of the Invention
The invention relates generally to field effect structures. More particularly, the invention relates to field effect structures with enhanced performance.
2. Description of the Related Art
As semiconductor fabrication technology has advanced and semiconductor device dimensions have decreased, a need to effectively and accurately control the dimensions of layers and regions that are used for fabricating semiconductor structures often becomes considerably more pronounced. To that end, an inadequate dimensional control when fabricating such layers and regions within semiconductor structures often provides for compromised performance of semiconductor devices that comprise the semiconductor structures.
While effective dimensional control of layers and regions is thus desirable within the semiconductor fabrication art, effective dimensional control is nonetheless not entirely without problems. Notably, dopant diffusion effects are often particularly detrimental with respect to dimensional control of doped semiconductor regions within semiconductor structures, since while as noted above semiconductor structure dimensions continue to decrease, a particular diffusion coefficient for a particular dopant within a particular semiconductor material is generally constant.
Various semiconductor structures having desirable properties are known in the semiconductor fabrication art.
For example, Furukawa et al., in U.S. Pat. No. 4,885,614, and Kuomoto et al., in U.S. Pat. No. 7,060,582, each teach the use of specific silicon-germanium alloy layer and silicon-germanium-carbon alloy layer combinations for avoiding misfit dislocations when fabricating bipolar transistor structures.
In addition Ismail et al., in EP 0 683 522 and U.S. Pat. No. 5,534,713, teaches a complementary metal oxide semiconductor field effect transistor structure that comprises a layered planar heterostructure that includes a tensile stressed silicon or silicon-germanium alloy layer, as well as a compressive stressed silicon-germanium alloy layer. The layered planar heterostructure provides for simultaneously optimized nFET performance and pFET performance within the complementary metal oxide semiconductor field effect transistor structure.
Further, each of: (1) Awano, in U.S. Pat. No. 4,994,866; (2) Canelaria et al., in EP 0 703 628; (3) Ek et al., in U.S. Pat. No. 5,667,586; (4) Kubo et al., in U.S. Pat. No. 6,674,100; (5) Koester, in U.S. Pub. No. 2005/0104092; and (6) Lee, in U.S. Pat. No. 7,145,166 teaches multilayer combinations that may under certain circumstances include silicon-germanium-carbon alloy layers for enhanced performance within semiconductor structures, including but not limited to semiconductor laser structures and metal oxide semiconductor field effect transistor structures.
Finally, Murota, et al., in U.S. Publication No. 2002/0109135 and Awano, in U.S. Pat. No. 6,885,041 each teach a metal oxide semiconductor field effect transistor structure that includes source and drain regions that may comprise different base semiconductor materials in comparison with channel regions within the metal oxide semiconductor field effect transistor structures, to effect enhanced performance of metal oxide semiconductor field effect transistor devices within the metal oxide semiconductor field effect transistor structures.
Semiconductor structure dimensions, and related semiconductor device dimensions, are certain to continue to decrease as semiconductor technology advances. Thus, desirable are semiconductor structures and semiconductor devices having enhanced performance at decreased dimensions, and methods for fabricating those semiconductor structures and semiconductor devices.